1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device in which data is electrically rewritable.
2. Description of the Related Art
An ETOX (trademark of Intel, Inc. in U.S.A.) type memory cell is well-known as a memory cell for a flash electrically erasable programmable read-only memory (EEPROM). A flash EEPROM using this ETOX type memory cell generally performs a writing operation on a bit basis. On the other hand, a flash memory EEPROM performs two kinds of erasure operations: that is to say, an erasure operation of a "chip simultaneous erasure type" in which a high voltage is simultaneously applied to the sources of all of the cell transistors on a chip and an erasure operation of a "block erasure type" in which a high voltage is selectively applied only to the sources of the cell transistors included in a selected block.
The structure of a cell transistor for the above-described ETOX type memory cell is shown in FIG. 20. In this cell transistor, a source 22 and a drain 23 are formed by providing two semiconductor regions having the polarities opposite to each other in the surface-layer portions of a semiconductor substrate 21. Between the source 22 and the drain 23, a floating gate 25 is formed over the semiconductor substrate 21 via a gate insulating film 24 and a control gate 27 is formed over the floating gate 25 via an interlevel insulating film 26.
When data is written into the cell transistor (or in the case of programming), a low voltage Vss (e.g., 0 V) is applied to the source 22, a voltage Vps (e.g., 6 V) is applied to the drain 23 and a high voltage Vpp (e.g., 12 V) is applied to the control gate 27. Then, hot electrons and hot holes are generated between the source 22 and the drain 23 of this cell transistor. Though the hot holes flow into the semiconductor substrate 21, the hot electrons are injected into the floating gate 25. Therefore, the threshold voltage of the cell transistor is increased, so that the data can be stored therein in a nonvolatile manner.
On the other hand, when the data is read out therefrom, a low voltage Vss (e.g., 0 V) is applied to the source 22, a voltage Vinl (e.g., 1 V) slightly higher than the voltage Vss is applied to the drain 23 and a voltage Vcc (e.g., 5 V) is applied to the control gate 27. Then, the amount of the current flowing between the source 22 and the drain 23 is varied in accordance with the threshold voltage of this cell transistor. Therefore, if the amount of this current is sensed and whereby the data is assumed to be detected as "1" when the amount is larger than a predetermined current value or as "0" when the amount is smaller than the predetermined current value, the data stored in the cell transistor can be read out.
Furthermore, when the data is erased therefrom, a high voltage Vpp is applied to the source 22, the drain 23 is opened (or turned into a floating state) and a low voltage Vss is applied to the control gate 27. Then, a Fowler-Nordheim (FN) tunneling current flows between the floating gate 25 and the source 22 through the gate insulating film 24, and thereby the electrons which have been accumulated in the floating gate 25 are emitted, so that the data is erased.
Since the flash EEPROM applies a high voltage Vpp to the source 22 of the cell transistor for erasing data, the flash EEPROM has the following disadvantages.
(a) Since it becomes necessary to improve the pressure tightness on the side of the source 22 to which a high voltage Vpp is applied, various measures are taken for such a purpose: e.g., the diffusion depth of a semiconductor region for the source 22 is made deeper than that of the drain 23 and the concentration of the impurities contained therein is reduced. As a result, it becomes difficult to reduce the size of such a device.
(b) When a high voltage Vpp is applied to the source 22, hot holes are generated in the vicinity of this source 22 and a part of these hot holes are trapped in the gate insulating film 24. As a result, a window narrow effect is generated in the threshold voltage, so that the reliability of the cell transistor is degraded.
(c) In the flash EEPROM, a simple source 22 is commonly used within a block. Therefore, if the erasure operation is performed by applying a high voltage Vpp to this source 22, a unit used for erasing the data becomes at least as large as the block and the erasure operation cannot be performed based on a unit smaller than this block.
In order to eliminate the above-described disadvantages, a "negative voltage erasure method" in which a negative voltage is applied to the control gate 27 for erasing the data is used, for example. In this negative voltage erasure method, a voltage Vps (e.g., 6 V) is applied to the source 22, the drain 23 is opened and a negative voltage Vbb (e.g., -10 V) is applied to the control gate 27. In such a case, an FN tunneling current also flows between the floating gate 25 and the source 22 through the gate insulating film 24 and the electrons which have been accumulated in the floating gate 25 are emitted, whereby the data is erased. In addition, since a high voltage is not applied to the source 22 in this negative voltage erasure method, it is no longer necessary to particularly improve the pressure tightness on the side of the source 22. Accordingly, this method can contribute to reducing the size of the device. Moreover, since the voltage Vps applied to the source 22 is a relatively low voltage of about 6 V, for example, almost no hot holes are generated, thereby preventing the reliability of the cell transistor from being degraded. Furthermore, since the erasure operation is performed on both the control gate 27 and the source 22, it is possible to perform a sector erasure operation based on a unit smaller than a block using a common source, e.g., on a word line basis.
In this negative voltage erasure method, a negative voltage is applied to a word line connected to the gate of the cell transistor. Therefore, if the drain of an n-channel MOSFET of a CMOS inverter circuit used for a general driver circuit is connected to the word line, a leakage current flows from the side of a p-type semiconductor substrate, on which this n-channel MOSFET is formed, to the drain. Thus, a circuit configuration, as shown in FIG. 21, in which a negative voltage decoder 33 using a driver circuit formed of a p-channel MOSFET alone for applying a negative voltage to this word line 31 is provided independent of a positive voltage decoder 32 using a CMOS inverter circuit including an n-channel MOSFET as a driver circuit for applying a positive voltage to the word line 31, and in addition, a p-channel MOSFET 34 for blocking the negative voltage Vbb is further provided between the word line 31 and the positive voltage decoder 32, has conventionally been proposed (see, for example, "Flash Memory using Word Negative Voltage Erasure Method", Technical Report of Institute of Electronics, Information and Communication Engineers ICD 9-135, pp. 9-14, 1991 and Japanese Laid-Open Patent Publication No. 3-219496 entitled "Nonvolatile Semiconductor Storage Device"). However, if such a p-channel MOSFET 34 for blocking the negative voltage Vbb is provided for the flash EEPROM, the following disadvantages are caused.
(a) In the case where the negative voltage Vbb is applied to the word line 31, it may be impossible to definitely turn OFF the p-channel MOSFET 34 by applying a low voltage Vss (e.g., 0 V) to the gate thereof. Therefore, since it is necessary to apply a voltage Vcc (e.g., 5 V) to the gate of the p-channel MOSFET 34, the stress applied to the gate insulating film becomes too large.
(b) Since the p-channel MOSFET 34 has a small transconductance gm representing various driving abilities such as a switching speed in a MOSFET, the operation speed thereof becomes lower. On the other hand, if the transconductance gm is to be increased, then it is necessary to enlarge the channel width of the p-channel MOSFET 34. However, if the channel width is enlarged, then the layout area occupied by the p-channel MOSFET 34 is adversely increased. That is to say, the delay time of the p-channel MOSFET 34 greatly depends upon the channel width of the p-channel MOSFET 34 as shown in FIG. 22. Therefore, if the channel width is enlarged, the delay time of the p-channel MOSFET 34 is shortened and a high-speed operation is realized. Nevertheless, the layout area occupied by this p-channel MOSFET 34 provided for each word line 31 is also increased.
In order to eliminate the above-described disadvantages, an invention has been proposed in which it is no longer necessary to provide the p-channel MOSFET 34 shown in FIG. 21 by instead outputting both a positive voltage and a negative voltage to the word line by the use of a driver circuit 1 formed of a CMOS inverter circuit as shown in FIG. 23 (see, for example, Japanese Laid-Open Patent Publication No. 5-28784). This driver circuit 1 is formed of a CMOS inverter circuit including a p-channel MOSFET 1a and an n-channel MOSFET 1b. The source of the p-channel MOSFET 1a is connected to an n-type semiconductor well forming this MOSFET. On the other hand, the source of the n-channel MOSFET 1b is connected to a p-type semiconductor well forming this MOSFET. The word line is connected to the output of this CMOS inverter circuit, i.e., the drain of the p-channel MOSFET 1a and the n-channel MOSFET 1b. In addition, a positive voltage ranging from a low voltage Vss to a high voltage Vpp is supplied from a positive voltage supply circuit 6 to the source of the p-channel MOSFET 1a in accordance with the operational mode. On the other hand, a low voltage Vss or a negative voltage Vbb is supplied from a negative voltage supply circuit 4 to the source of the n-channel MOSFET 1b in accordance with the operational mode. The input of this CMOS inverter circuit is connected to the output of a NAND circuit 7a of an address decoder 7 for decoding an externally input address signal.
In the case where a negative voltage Vbb is supplied from the negative voltage supply circuit 4 to the driver circuit 1 having such a configuration, this negative voltage Vbb is applied not only to the source of the n-channel MOSFET 1b but also to the p-type semiconductor well. As a result, a forward bias is caused between the p-type semiconductor well and the source, thereby preventing the leakage current from flowing. Consequently, not only the above-described disadvantage can be eliminated since the p-channel MOSFET 34 shown in FIG. 21 for blocking the negative voltage Vbb is no longer necessary to be provided, but also the positive voltage decoder 32 and the negative voltage decoder 33 can be integrally formed, so that the circuit size can also be reduced. Nevertheless, in order to apply the negative voltage Vbb to the p-type semiconductor well forming the n-channel MOSFET 1b thereon in such a manner, it is necessary to electrically isolate the p-type semiconductor well from the p-type semiconductor substrate by providing an n-type semiconductor well therebetween.
However, since a conventional circuit shown in FIG. 23 corresponds to a case where data is erased mainly on a chip basis or on a block basis, it is adversely difficult for such a circuit to correspond to a sector erasure method or the like in which only the data stored in a memory cell connected to an erasure unit smaller than a chip or a block (e.g., a word line) is erased by making full use of the advantages of the negative voltage erasure method.
FIG. 24 shows a circuit enabling a sector erasure operation for performing an erasure operation on a word line basis that utilizes the circuit configuration shown in FIG. 23. In this circuit, not only the NAND circuit 7a but also another NAND circuit 7b for decoding an address signal in a similar manner and a negative voltage switching circuit 7c for switching the negative voltage Vbb in accordance with the output of the NAND circuit 7b are provided for the address decoder 7. The negative voltage Vbb output from the negative voltage supply circuit 4 is to be supplied to the source of the n-channel MOSFET 1b of the driver circuit 1 via the negative voltage switching circuit 7c. In the case where an erasure signal W/E-bar is at an L level (in the erasure mode), when the output level of the NAND circuit 7b becomes L (selection), the negative voltage switching circuit 7c outputs the negative voltage Vbb supplied from the negative voltage supply circuit 4 and when the output level of the NAND circuit 7b becomes H (non-selection), the negative voltage switching circuit 7c outputs a low voltage Vss or a voltage Vinh slightly higher than Vss. On the other hand, in the case where the erasure signal W/E-bar is at an H level (in the writing mode and the reading mode), the negative voltage switching circuit 7c outputs a low voltage Vss. Consequently, in the erasure mode, the negative voltage Vbb is supplied only to the driver circuit 1 selected based on the address signal and can be output through the n-channel MOSFET 1b of this driver circuit 1 to the word line. As a result, an erasure operation can be performed on a word line basis.
However, one driver circuit 1 and one address decoder 7 are required to be provided for every word line in the circuit shown in FIG. 24. Therefore, assuming that there are 512 word lines, it is necessary to provide 512 driver circuits 1 and 512 address decoders 7, so that the layout area occupied by these circuits adversely becomes too large.
Furthermore, since the negative voltage Vbb is applied only to the p-type semiconductor well of the n-channel MOSFET 1b of the selected driver circuit 1 in the circuit shown in FIG. 24, the n-channel MOSFETs 1b of the respective driver circuits 1 are required to be formed over the p-type semiconductor wells which are electrically isolated from each other. Therefore, the layout area occupied by the driver circuits 1 also becomes too large.